The present invention relates to a pre-driver for an output buffer.
CMOS output buffers are widely used to drive external capacitive loading or external resistive loading, sometimes over a long distance. A CMOS output buffer usually includes a pull-up PMOS transistor and a pull-down NMOS transistor. The loading values for CMOS output buffers can vary across different applications. For this reason, it is required that the pull-up PMOS transistor and the pull-down NMOS transistor have high driving strengths, which are usually accomplished by large sizes in the PMOS and NMOS transistors.
The large sizes in the PMOS and NMOS transistors, however, create two major drawbacks for CMOS output buffers at the same time. One drawback is that when the output buffer switches voltage logic levels (from low to high, or vice versa), large current transient can pass through the bonding wires and create large power/ground bouncing noise or output bouncing noise. The voltage of bouncing noise can be characterized by the following equation:V=L dl/dT   (1)Slew rate=dV/dT   (2)where L is the inductance of the bonding wire and/or the inductance from the PCB trace, I is the instantaneous current at time T, and V is the voltage induced by the instantaneous current across the inductor L at time T. dV/dT is referred to as the slew rate of the output buffer which is the rising or falling rate of the output voltage of the output buffer. If the voltage spike induced exceeds a logic threshold of the chip connecting to the output buffer during a logic level change, a logic fault will be created, which produces wrong data transmission. In order to minimize the voltage spike, conventional output buffers can include features for controlling the slew rate dV/dT and minimizing the voltage spike. One such feature includes a number of parallel transistors that can be sequentially turned on through delay elements to reduce the instantaneous current in the output buffer.
Another drawback associated with the large sizes of the PMOS and NMOS transistors is the large crow-bar current (shoot-through current) that can be produced between the voltage supply nodes VDD and VSS when the output buffer switches logic levels. During a logic level switch, it is likely that both the PMOS transistor and the NMOS transistor in the output buffer are turned on simultaneously, which can cause a large amount of current flowing through from VDD to VSS through the PMOS and the NMOS transistors. This current is called crowbar current (or shoot-through current). The crowbar current can increase dynamic current consumption, and shorten the battery lifetime for chips in portable devices.
Attempts have been made in output buffer designs to alleviate the above described drawbacks. U.S. Pat. No. 5,231,311 discloses a circuit having crowbar current control and slew rate control in an output buffer. However, the circuit includes an RC network with large resistor values to have good slew rate control between parallel PMOS transistors and NMOS transistors. The quick turn-off of the output buffer is accomplished by the diode bypass network. The turn-off of the output buffer is tied to VDD−VTHP for PMOS output transistors and VSS+VTHN for NMOS output transistors until the RC delayed gate node reaches VDD and VSS, respectively. Thus the pull-up/pull-down output transistors can operate below threshold for a short period of time while the pull-down/pull-up output transistors start operating. For such reason, it can be difficult to select the resistor values for resistors in the RC network.
U.S. Pat. Nos. 7,208,984, 6,653,873, and 6,570,414 describe methods for reducing crowbar currents without simultaneous slew rate control. U.S. Pat. Nos. 7,019,551 and 6,992,511 address controlling slew rates of output buffers but do not provide crowbar current control at the same time.
There is therefore a need to simultaneously address both above described drawbacks at the same time. It is also desirable for a design solution that is simple to implement and area efficient.